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CY7C1021CV33
64K x 16 Static RAM
Features
* Pin- and function-compatible with CY7C1021BV33 * High speed -- tAA = 8, 10, 12, and 15 ns * CMOS for optimum speed/power * Low active power -- 360 mW (max.) * Data retention at 2.0V * Automatic power-down when deselected * Independent control of upper and lower bits * Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021CV33 is available in standard 44-pin TSOP Type II 400-mil-wide SOJ packages, as well as a 48-ball FBGA.
Functional Description
The CY7C1021CV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A7 A6 A5 A4 A3 A2 A1 A0
64K x 16 RAM Array 512 X 2048
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
ROW DECODER
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
CY7C1021CV33-8 8 95 5 CY7C1021CV33-10 10 90 5 CY7C1021CV33-12 12 85 5 CY7C1021CV33-15 15 80 5 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05132 Rev. *C
A8 A9 A10 A11 A12 A13 A14 A15
*
SENSE AMPS
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised October 30, 2002
CY7C1021CV33
Pin Configuration
48-ball FBGA
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O 10 I/O 11 I/O12 I/O13 NC A8 (Top View) 4 3 A0 A3 A5 NC NC A14 A12 A9 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O2 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O1 VCC VSS I/O6 I/O7 NC A B C D E F G H
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CY7C1021CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ......................................-0.5V to VCC+0.5V DC Input Voltage[1] ...................................-0.5V to VCC+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current GND < VI < VCC Output Leakage Current GND < VI < VCC, Output Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 1021CV33-8 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 95 2.0 -0.3 -1 -1 Max. 1021CV33-10 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 90 2.0 -0.3 -1 -1 Max. 1021CV33-12 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 85 2.0 -0.3 -1 -1 Max. 1021CV33-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 -300 80 Max. Unit V V V V A A mA mA
Output Short Circuit VCC = Max., Current[2] VOUT = GND VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
ISB1
15
15
15
15
mA
ISB2
5
5
5
5
mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1021CV33
AC Test Loads and Waveforms[4]
8-ns devices: OUTPUT
10-, 12-, 15-ns devices: Z = 50 50 3.3V
R 317
30 pF*
OUTPUT 30 pF R2 351
* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT
1.5V
(a)
(b)
High-Z characteristics: R 317 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF R2 351
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Note: 4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
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CY7C1021CV33
Switching Characteristics Over the Operating Range[5]
1021CV33-8 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[8] tPD[8] tDBE tLZBE tHZBE Write Cycle[9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low-Z[6] WE LOW to High-Z[6, 7] Byte Enable to End of Write 6 8 7 7 0 0 6 5 0 3 4 7 10 8 8 0 0 7 5 0 3 5 8 12 9 9 0 0 8 6 0 3 6 9 15 10 10 0 0 10 8 0 3 7 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z CE LOW to
[6]
1021CV33-10 Min. 10 Max.
1021CV33-12 Min. 12 Max.
1021CV33-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 7 0 7 ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 8
Max.
8 3 8 5 0 4 3 4 0 8 5 0 4 0 0 3 0 3
10 3 10 5 0 5 3 5 0 10 5 0 5
12 12 6 6 6 12 6 6
OE HIGH to High-Z[6, 7] Low-Z[6] CE HIGH to High-Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. This parameter is guaranteed by design and is not tested. 9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
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CY7C1021CV33
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 11. WE is HIGH for Read cycle. 12. Address valid prior to or coincident with CE transition LOW.
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CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [13, 14]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE t BW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes: 13. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O9-I/O16 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY7C1021CV33
Ordering Information
Speed (ns) 8 Ordering Code CY7C1021CV33-8VC CY7C1021CV33-8ZC CY7C1021CV33-8BAC 10 CY7C1021CV33-10VC CY7C1021CV33-10VI CY7C1021CV33-10ZC CY7C1021CV33-10ZI CY7C1021CV33-10BAC CY7C1021CV33-10BAI 12 CY7C1021CV33-12VC CY7C1021CV33-12VI CY7C1021CV33-12ZC CY7C1021CV33-12ZI CY7C1021CV33-12BAC CY7C1021CV33-12BAI 15 CY7C1021CV33-15VC CY7C1021CV33-15VI CY7C1021CV33-15ZC CY7C1021CV33-15ZI CY7C1021CV33-15BAC CY7C1021CV33-15BAI BA48A 48-ball FBGA Z44 44-lead TSOP Type II V34 44-lead (400-Mil) Molded SOJ BA48A 48-ball FBGA Z44 44-lead TSOP Type II V34 44-lead (400-Mil) Molded SOJ BA48A 48-ball FBGA Z44 44-lead TSOP Type II Package Name V34 Z44 BA48A V34 Package Type 44-lead (400-Mil) Molded SOJ 44-lead TSOP Type II 48-ball FBGA 44-lead (400-Mil) Molded SOJ Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
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CY7C1021CV33
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
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CY7C1021CV33
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05132 Rev. *C Page 11 of 12
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33 64K x 16 Static RAM Document Number: 38-05132 REV. ** *A *B *C ECN NO. 109472 115044 115808 120413 Issue Date 12/06/01 05/08/02 06/25/02 10/31/02 Orig. of Change HGK HGK HGK DFP New Data Sheet Ram7 version C4K x 16 Async. Remove "Preliminary" ISB1 and ICC values changed Updated BGA pin E4 to NC. Description of Change
Document #: 38-05132 Rev. *C
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